The present invention relates generally to the transfer of signals in logic circuits and, more specifically, to a balanced transfer gate circuit having a switching speed that is independent of the order in which individual series connected transfer gates are activated.
In the design of logic circuits, particularly in the area of semiconductor memories, pass or transfer gates are utilized in a variety of applications to selectively transfer signals from one portion of a circuit to another. A typical transfer gate includes a p-channel metal oxide semiconductor (PMOS) transistor and an n-channel metal oxide semiconductor (NMOS) transistor having their drains coupled together to form an input, their sources coupled together to form an output, and the gates of the respective transistors receiving complementary control clock signals. The transfer gate couples its input to its output in response to the control clock signals, and thus operates as an electronic switch to transfer a signal placed on its input to its output. By utilizing both PMOS and NMOS transistors, the voltage level of signals that can be transferred by the transfer gate is not limited by the threshold voltages of the transistors.
The switching time of a transfer gate is the time it takes to transfer a signal from the input to the output. The switching time is a function of a number of factors including the gate-to-source and drain-to-source junction capacitances, and the channel resistance of the [MOS] metal oxide semiconductor (MOS) transistors. In addition, the switching time is a function of the load presented by circuitry coupled to the output of the transfer gate. When a number of transfer gates are connected in series, the output of an individual transfer gate may be loaded by other transfer gates in the series connected circuit. The load presented by such other transfer gates varies as the other transfer gates are selectively activated and deactivated. In addition, the load presented on the output of an individual transfer gate is a function of the order in which the other transfer gates are activated. For example, if four transfer gates are connected in series, the load presented on the output of the second transfer gate depends on whether transfer gates three and four are activated or deactivated, and the order in which they are activated.
FIG. 1 is a schematic of a conventional switching circuit 10 including two series-connected transfer gates 12 and 14. The transfer gate 12 receives a pair of complementary clock signals CLK0 and {overscore (CLK0)}, and couples its input IN to its output when the signals CLK0 and {overscore (CLK0)} are high and low, respectively. The transfer gate 14 receives a pair of complementary clock signals CLK1 and {overscore (CLK1)}, and couples its input to its output OUT when the signals CLK1 and {overscore (CLK1)} are high and low, respectively. When both the clock signals CLK0 and CLK1 are high, the transfer gates 12 and 14 are activated, coupling the input IN to the output OUT. If either of the signals CLK0 and CLK1 is low, one of the transfer gates 12 or 14 is turned OFF isolating the input IN from the output OUT.
During operation of the switching circuit 10, external circuitry (not shown in FIG. 1) develops the clock signals CLK0 and CLK1 to control activation of the transfer gates 12 and 14. The external circuitry may at times activate the transfer gate 12 before the transfer gate 14, and at other times the reverse will be true. The switching speed of the switching circuit 10 is the time it takes for a signal on the input IN to be coupled to the output OUT. Ideally, the switching speed is independent of the order in which the transfer gates 12 and 14 are activated. In the circuit 10, however, the switching speed depends upon which transfer gate 12 or 14 is activated first. This is true because when the transfer gate 14 is activated first, the transfer gate 12 drives the load on the output OUT through the activated transfer gate 14, and when the transfer gates 12 and 14 are activated in the reverse order, the transfer gate 14 directly drives the load on the output OUT. For example, assume both transfer gates 12 and 14 are initially deactivated so the input IN is isolated from the output OUT. Further assume the signal on the input IN is high. When the transfer gate 12 is activated, the high input signal is coupled to the output of the transfer gate 12. When the transfer gate 14 is thereafter activated it must drive the load presented on the output OUT in order to drive the output OUT high. In contrast, when the transfer gate 14 is activated first, the transfer gate 12 can drive the load presented on the output OUT through the channel resistance impedance of the transfer gate 14. Thus, when the load on the output OUT is capacitive, for example, the additional impedance of the transfer gate 14 and corresponding increased RC time constant result in the output OUT going high more slowly.
There is a need for a switching circuit including a number of series-connected transfer gates in which the switching speed of the switching circuit is independent of the sequence in which the transfer gates are activated.
A balanced switching circuit comprises a plurality of switch circuits, each switch circuit having an input terminal, an output terminal, and at least one control terminal adapted to receive a control signal. Each switch circuit is operable to couple the input terminal to the output terminal in response to the control signal. The plurality of switch circuits are arranged in N rows and N columns with the input and output terminals of the N switch circuits in each row connected in series between a first signal terminal and a second signal terminal. Each switch circuit in a given column has its control terminal connected to one of N clock terminals adapted to receive respective clock signals. Further, each clock terminal is coupled to the control terminal of only one switch circuit in each row and one switch circuit in each column. The balanced switching circuit is operable to couple the first signal terminal to the second signal terminal in response to the clock signals.